M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 206

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.156. Full-status check flowchart
Rev.2.00
REJ03B0005-0200
Full-Status Check
Erase status (SR5)
The erase status indicates the operating status of an auto erase to the CPU. It is set to "1" when an erase error
occurs. The erase status is reset to "0" when cleared.
Program status (SR4)
The program status indicates the operating status of an auto write to the CPU. It is set to "1" when a write error
occurs. The program status is reset to "0" when cleared.
When an erase command is in error, which occurs if the command entered after the block erase command (20
is not the confirmation command (D0
If the program status or erase status = "1", the following commands entered by command write are not accepted
and SR4 and SR5 are set to "1" (command sequence error):
(1) A valid command is not entered correctly
(2) The data entered in the second bus cycle of lock bit program (77
unlocked blocks (A7
command that has been set up in the first bus cycle is canceled.
Block status after program (SR3)
If data is overwritten (this occurs when a memory cell becomes overcharged and data incorrectly read), "1" is set
for the program status after the program at the end of the page write operation. In other words:
• When writing ends successfully, "80
• When writing fails, "90
• When excessive data is written, "88
A full-status check allows the user to review the erase and program operations. Figure 1.156 shows a full-status
check flowchart and the action to take when an error occurs.
Oct 16, 2006
End (block erase, program)
page 204 of 264
Read status register
SR4=1 and
SR5=1 ?
SR5=0?
SR4=0?
SR3=0?
16
/D0
YES
YES
YES
NO
16
16
" is output;
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all
YES
) is not the D0
NO
NO
NO
unlocked blocks and lock bit program commands are accepted. Execute the clear
status register command (50
Program error (page
Block erase error
sequence error
Program error
Command
or lock bit)
(block)
16
16
16
" is output.
), both the program status and erase status (SR5) are set to "1".
" is output;
16
or FF
16
Execute the clear status register command (50
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
cannot be used.
Execute the read lock bit status command (71
see if the block is locked. After removing the lock,
execute a write operation the same way. If the error still occurs,
the page in error cannot be used.
After erasing the block in error, exectue the operation again.
If the same error still occurs, the block in error cannot
be used.
If a block erase error occurs, the block in error
) before executing these commands.
16
. However, if FF
16
16
/D0
is entered, read array is assumed and the
16
), block erase (20
16
16
) to
)
CPU Rewrite Mode
16
/D0
16
), or erase all
16
)