M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 16

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Program counter (PC)
Interrupt table register (INTB)
Stack pointer (USP/ISP)
Static base register (SB)
Flag register (FLG)
Oct 16, 2006
• Bit 0: Carry flag (C flag)
• Bit 1: Debug flag (D flag)
• Bit 2: Zero flag (Z flag)
• Bit 3: Sign flag (S flag)
• Bit 4: Register bank select flag (B flag)
• Bit 5: Overflow flag (O flag)
• Bit 6: Interrupt enable flag (I flag)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
The stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each
configured with 16 bits.
The desired type of stack pointer (USP or ISP) can be selected by the stack pointer select flag (U flag).
This flag is located at bit 7 of the flag register (FLG).
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.7 shows the flag register
(FLG). The following explains the function of each flag:
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
This flag enables a single-step interrupt.
When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to
"0" when the interrupt is acknowledged.
This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0".
This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0".
This flag chooses a register bank. Register bank 0 is selected when this flag is "0"; register bank 1 is
selected when this flag is "1".
This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0".
This flag enables all maskable interrupts.
Interrupts are disabled when this flag is "0", and are enabled when this flag is "1". This flag is cleared to
"0" when an interrupt is acknowledged.
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Central Processing Unit