M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 230

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.184. Timing for reading the status register
Figure 1.185. Timing for clearing the status register
Figure 1.186. Timing for reading lock bit status
Rev.2.00
REJ03B0005-0200
5. Read Status Register Command
This command reads the status information. When the "70
the status register (SRD) are read with the 2nd byte and the contents of status register 1 (SRD1) are read with the 3rd
byte. Figure 1.184 shows the read status register timing.
6. Clear Status Register Command
This command clears the bits (SR3–SR5) that are set when an erase, program or status operation ends in error. When
the "50
register timing.
7. Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Figure 1.186 shows the read lock bit status timing. To
execute the read lock bit status command:
(1) Transfer the "71
(2) Transfer addresses A
(3) The lock bit data of the specified block is output with the 4th byte. The 6th bit (D
Write the highest address of the specified block for addresses A
Oct 16, 2006
16
" command code is sent with the 1st byte, the SR3-SR5 bits are cleared. Figure 1.185 shows the clear status
(M30245 reception data)
(M30245 transmit data)
16
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" command code with the 1st byte.
(M30245 reception data)
(M30245 transmit data)
8
to A
(M30245 reception data)
(M30245 transmit data)
15
and A
RxD1
TxD1
16
to A
RxD1
TxD1
23
RxD1
with the 2nd and 3rd bytes respectively.
TxD1
71
16
70
16
16
" command code is sent with the 1st byte, the contents of
A
A
8
15
50
8
to
output
SRD
to A
16
23
A
A
16
.
23
to
output
SRD1
6
) of the output data is the lock bit data.
D6
Serial I/O Mode 2