M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 70

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Watchdog Timer
The watchdog timer can detect a runaway program. It is a 15-bit counter that decrements using the clock derived
from dividing the BCLK by the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the
watchdog timer. The watchdog timer interrupt is a non-maskable interrupt.
When X
prescaler divide ratio to be either 16 or 128. When X
regardless of WDC7. The watchdog timer cycle can be calculated as follows:
When X
Watchdog timer period = prescaler dividing ratio (16 or 128) X Watchdog timer count (32768)
When X
Watchdog timer period = prescaler dividing ratio (2) X Watchdog timer count (32768)
Example:
When BCLK is 12 MHz and the prescaler divide ratio is set to 16, the monitor timer cycle is approximately 43.69 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E
watchdog timer interrupt request is generated.
The prescaler is initialized only when the microcomputer is reset. After a reset, the watchdog timer and prescaler
are both stopped. The count is started by writing to the watchdog timer start register (address 000E
The watchdog timer and the prescaler stop in stop mode, wait mode, and hold state. After exiting these modes,
counting starts from the remaining value. Figure 1.42 shows the block diagram of the watchdog timer. Figure 1.43
shows the watchdog timer-related registers.
Oct 16, 2006
IN
IN
CIN
chosen for BCLK:
is selected for BCLK, bit 7 (WDC7) of the watchdog timer control register (address 000F
chosen for BCLK:
page 68 of 264
BCLK
BCLK
CIN
is selected for BCLK, the prescaler divide ratio is set to 2
Watchdog Timer
16
16
), and when a
16
) selects the
).