M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 108

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.74. An example of DMA transfer by external factors
Rev.2.00
REJ03B0005-0200
Internal factors
External factors
Priorities of the channels and DMA transfer timing
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an
internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to
several factors.
Turning the DMA request bit to "1" due to an internal factor is timed to be effected immediately before the transfer
starts.
An external factor is a DMA request caused from the INTi pin input edge ("i" reflects the DMAC channel used).
Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to
become the DMA transfer request signals.
The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge
applicable to the function specified by the DMA request factor selection bit (synchronizes with the trailing edge of the
input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data transfer starts
similarly to the state in which an internal factor is selected.
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading
edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn to "1". If the channels
are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives
the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus
right to the CPU. The DMA priority levels are:
DMA0 > DMA1 > DMA2 > DMA3
Figure 1.74 is an example of DMA transfer effected by external factors when DMA0 and DMA1 requests occur in the
same sampling cycle.
Oct 16, 2006
DMA0
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Example of DMA transmission that is carried out in minimum cycles
at the time DMA transmission occur concurrently.
page 106 of 264
/////////////////
///////////
///////
///////////
//////////////
Bus
control
DMA