M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 93

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.58. USB Endpoint x IN Control & Status register (EPxICS)
Rev.2.00
REJ03B0005-0200
USB Endpoint x IN Control and Status register
(b15)
0
b7
• INxCSR6 (FLUSH):
The CPU writes a "1" to this bit to flush the IN buffer.
• When there is one data set in the IN buffer, a flush causes the IN buffer to be empty.
• When there are two data sets in the IN buffer, a flush causes the older data set to be flushed out from the IN buffer.
The USB FCU updates the buffer status bits the same way as a data set is transmitted to the host when it sees a
FLUSH. Setting the FLUSH bit during transmission could produce unpredictable results.
• INxCSR7 (INTPT):
The CPU writes a "1" to this bit to initialize the endpoint as a rate feedback interrupt endpoint.
• INxCSR8 (ISO):
The CPU writes a "1" to this bit to set the endpoint as an isochronous data transfer endpoint.
• INxCSR9 (SEND_STALL):
The CPU writes a "1" to this bit when the endpoint is stalled (transmitter halt). The USB FCU returns STALL handshakes
while this bit is set. The CPU writes a "0" to clear this bit, If the STALL condition no longer exists.
• INxCSR10 (AUTO_SET):
The CPU writes a "1" to this bit to enable the AUTO_SET function. AUTO_SET takes place only when a data packet that
is equal to MAXP (or data set that is equal to BUF_SIZ, in continuous mode) is loaded to the buffer. See "IN (Transmit)
FIFO" operation for details.
0 0 0 0
Oct 16, 2006
(b8)
b0
b7
page 91 of 264
b0
Note: Always read a "0"
Bit Symbol
INxCSR0
INxCSR1
INxCSR2
INxCSR3
INxCSR4
INxCSR5
INxCSR6
INxCSR7
INxCSR8
INxCSR9
INxCSR10
Reserved
Symbol
EPxICS (x = 1 - 4)
IN_BUF_STS0 flag
IN_BUF_STS1 flag
UNDER-RUN flag
SET_IN_BUF_RDY
CLR_UNDER_RUN
TOGGLE_INT
FLUSH
INTPT
ISO
SEND_STALL
AUTO_SET
Bit Name
029E
02AA
Address
16
16
These two bits indicate the EPx IN buffer status
Bit1
0
0
1
1
0 : No underrun detected
1 : Underrun detected
0 : No action
1 : Data set loaded to the IN buffer (updates IN buffer status flags)
0 : No action
1 : Clears UNDER_RUN flag
0 : No action
1 : Initialize the next data PID as a DATA0 for transmission
0 : No action
1 : Flush out one data set
0 : Select non-rate feedback interrupt transfer
1 : Select rate feedback interrupt transfer
0 : Select non-isochronous endpoint
1 : Select isochronous endpoint
0 : No STALL by CPU
1 : STALL by CPU
0 : AUTO_SET disabled
1 : AUTO_SET enabled
Must always be set to "0"
, 02A4
, 02B0
16
16
Bit0
0 : No data set in the IN buffer
1 : Single buffer mode: N/A
0 : Single buffer mode: N/A
1 : Single buffer mode: one data set in the IN buffer
,
Double buffer mode: one data set in the IN buffer
Double buffer mode: N/A
Double buffer mode: two data sets in the IN buffer
Function
When reset
0003
16
Universal Serial Bus
O X
O O
R W
O O
O O
O X
O X
O O
O O
O O
Note
O O
O O
O O
Note
Note
Note