M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 141

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Figure 1.98. Typical transmit timings in UART mode
Oct 16, 2006
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (TI)
CTSi
TxDi
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
Transfer clock
Transmit buffer
empty flag (TI)
Transmit interrupt
request bit (IR)
Transmit enable
bit (TE)
TxDi
Transmit register
empty flag (TXEPT)
Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
•
•
•
•
Parity is enabled.
Transmit interrupt cause select bit = "1".
The above timing applies to the following settings :
One stop bit.
CTS function is selected.
• Parity is disabled.
• Two stop bits.
• TCS function is disabled.
• Transmit interrupt cause select bit = "0".
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"H"
"1"
"0"
"1"
"0"
"L"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Start
Start
ST
ST
bit
Data is set in UARTi transmit buffer register
bit
Cleared to "0" when interrupt request is accepted, or cleared by software
D
D
Data is set in UARTi transmit buffer register.
0
0
D
D
1
1
Tc
D
D
2
2
D
D
3
3
Tc
D
D
4
4
The transfer clock stops momentarily as CTS is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to "L".
Transferred from UARTi transmit buffer register to UARTi transmit register
D
D
5
5
D
D
6
6
Transferred from UARTi transmit buffer register to UARTi transmit register
D
D
Tc = 16 (m + 1) / fi or 16 (m + 1) / f
Parity
7
7
bit
D
P
fi : frequency of BRGi count source (f
f
m : value set to BRGi
8
EXT
Stop
Cleared to "0" when interrupt request is accepted, or cleared by software
bit
Tc = 16 (m + 1) / fi or 16 (m + 1) / f
SP
Stop
SP
bit
: frequency of BRGi count source (external clock)
SP
fi : frequency of BRGi count source (f
f
m : value set to BRGi
EXT
Stop
ST
bit
ST
: frequency of BRGi count source (external clock)
D
D
Clock asynchronous serial I/O (UART) mode
0
0
D
D
1
1
D
D
2
2
Stopped pulsing because transmit enable bit = "0"
D
D
3
3
EXT
D
D
4
4
D
D
5
5
EXT
1
D
, f
D
6
8
6
, f
D
D
32
7
7
1
, f
)
P SP
D
8
8
, f
SPSP
32
)
ST
ST
D
0
D
D
0
1
D
1