M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 73

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
The USB Function Interrupt has multiple interrupt sources that can be enabled within the USB Function Interrupt Enable
Register (USBIE).
EP0 Interrupt
USB Function Interrupt
USB Reset Interrupt
USB Resume Interrupt
USB SOF Interrupt
The EP0 interrupt is generated when one of the following events occur:
• A data set is successfully received
• A data set is successfully sent
• EP0CSR3 (DATA_END) flag is cleared. This event is maskable and the default is masked.
• A control transfer ends prematurely (i.e., the USB FCU sets the SETUP_END bit).
The USB Function interrupt can be triggered by:
• The interrupts from eight endpoints (EP1-EP4 IN/OUT). The interrupts indicate if a data set was either sent or received.
• A data flow error from any of the nine endpoints (including EP0)
• The enabling of any IN endpoint (EP1-EP4 IN).
• The corruption of the final ACK of a Control Read transfer's Data Stage.
Each endpoint interrupt is enabled by setting the corresponding bit in the USB Interrupt Enable register (USBIE).
Interrupt status flags associated with each source are contained in USB Interrupt Status register (USBIS).
A USB Reset Interrupt is generated when the USB Function Control Unit (USB FCU) sees a SE0 present on D+/D- for
at least 2.5us. When a reset signal is detected by the USB FCU, an internal reset pulse is also generated to reset all
USB internal registers to the default values.
When the CPU recognizes a USB Reset Interrupt, it re-initializes the USB FCU to ensure that the USB operation
functions properly.
The USB Reset Interrupt Control register (RSTIC) contains the USB Reset Interrupt request bit and interrupt priority
select bits used to enable the interrupt and set the software priority level.
A USB Resume Interrupt is generated when the USB FCU is in the suspend state and detects non-idle signaling on
the D+/D-.
The USB Resume Interrupt Control register (RSMIC) contains the USB Resume Interrupt request bit and interrupt
priority select bits used to enable the interrupt and set its software priority level.
The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU generates
a USB SOF Interrupt request when a start-of-frame packet is received.
Because the start-of-frame packet could be corrupted, a new frame might start without successful reception of the
SOF packet. For this reason, an artificial SOF is provided. The frame timer signals a time out when a SOF packet is
not received within the allotted time. The device generates an SOF interrupt once every frame. Setting bit 2 of the
USB ISO Control Register to a "1" enables the artificial SOF function.
Register SOFIC contains the USB SOF Interrupt’s request bit and interrupt priority select bits that are used to enable
the interrupt and set its software priority level.
Oct 16, 2006
page 71 of 264
Universal Serial Bus