M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 170

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Table 1.56. A/D Converter performance
Rev.2.00
REJ03B0005-0200
Note 1: Doesnot depend on use of sample and hold function.
Note 2: Whenf(Xin) is over 10 MHz, the ΦAD frequency must be set under 10MHz with the frequency select bits (bits
Note 3: Set the port direction register to input.
A/D conversion method
Analog input voltage
(Note 1)
Operating clock ΦAD
(Note 2)
Resolution
Non-linear accuracy
Operating modes
Analog input pins
A/D conversion start
condition
Conversion speedper
pin
A/D converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. Pins P10
with A/D conversion to input. The result of an A/D conversion is stored in the AD registers of the selected pins.
Table 1.56 shows the performance of the A/D converter. Figure 1.125 shows the block diagram of the A/D converter, and
Figure 1.126 and Figure 1.127 show the A/D converter-related registers.
7 at 03D6
Without the sample and hold function, set the ΦAD to 250kHz or higher.
With the sample and hold function, set the ΦAD frequency to 1 MHz or higher.
Oct 16, 2006
Item
16
and bit 4 at 03D7
0
to P10
page 168 of 264
•
•
•
Successive approximation (capacitive coupling amplifier)
0V to AVcc (Vcc)
f
8-bit or 10-bit (selectable)
• One-shot mode
•
•
•
8 pins (AN
•
•
AD
Repeat mode
Single sweep mode
Repeat sweep mode 0
Repeat sweep mode 1
Software trigger
External trigger (canberetriggered)
Without sample and hold function
With sampleand hold function
10-bit resolution: 33 ΦAD cycles
-A/D conversion startswhen the A/D conversion start flag changes to "1"
-A/D conversion startswhen AD
8-bit resolution: 49 ΦAD cycles
10-bit resolution: 59 ΦAD cycles
8-bit resolution: 28 ΦAD cycles
, f
7
AD
function as the analog signal input pins. Set the direction registers corresponding to a pin
/2, f
16
0
AD
).
to AN
/3, f
AD
7
/4
)
fAD=f(Xin)
TRG
Performance
/P9
3
input changes from "H" to "L" (Note 3)
A/D converter