M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 46

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Table 1.26. System clock control registers 0 and 1 operating mode settings
Rev.2.00
REJ03B0005-0200
Invalid
Invalid
Invalid
CM17
• Divide by 2 mode
• Divide by 4 mode
• Divide by 8 mode
• Divide by 16 mode
• No-division mode
• Low-speed mode
• Low power dissipation mode
The main clock is divided by 2 to obtain the BCLK.
The main clock is divided by 4 to obtain the BCLK.
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the
user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock oscillator
must be stable. When going to low-speed or lower power consumption mode, make sure the subclock's oscillator is
stable.
The main clock is divided by 16 to obtain the BCLK.
The main clock is divided by 1 to obtain the BCLK.
fc is used as the BCLK.
Note: Oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or
vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, write the program to wait until this
clock has stabilized after powering up and after returning from stop mode.
fc is the BCLK and the main clock is stopped.
Note: Before the count source for BCLK can be changed from X
must first be stable. Allow some wait time in software for the oscillation to stabilize before switching the clock over.
0
1
1
0
Oct 16, 2006
Invalid
Invalid
Invalid
CM16
1
0
1
0
page 44 of 264
CM07
0
0
0
0
0
1
1
Invalid
Invalid
CM06
0
0
1
0
0
CM05
0
0
0
0
0
0
1
IN
Invalid
Invalid
Invalid
Invalid
Invalid
to X
CM04
1
1
CIN
or vice versa, the new count source's oscillator
Divide-by-2 mode
Divide-by-4 mode
Divide-by-8 mode
Divide-by-16 mode
No division mode
Low-speed mode
Low power dissipation mode
BCLK operating mode
System Clock