ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 104

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

9.3
9.3.1
9.3.2
9.3.3
9.4
9.4.1
8077H–AVR–12/09
Reset Sequence
Reset Sources
Reset Counter Delay
Oscillator Startup
Oscillator Calibration
Power-On Reset
Reset request from any reset source immediately reset the device, and keep it in reset as long
as the request is active. When all reset requests are released, the device will go through three
stages before the internal reset is released and the device starts running.
If one of the reset request occur during this, the reset sequence will start over again.
The Reset Counter Delay is the programmable period from all reset requests are released and
until the reset counter times out and releases reset. The Reset Counter Delay is timed from the
1 kHz output of the Ultra Low Power (ULP) Internal Oscillator, and the number of cycles before
the timeout is set by the STARTUPTIME fuse bits. The selectable delays are shown in
1.
Table 9-1.
After the Reset Counter Delay, the default clock is started. This is the 2 MHz internal RC oscilla-
tor, and this uses 6 clock cycles to startup and stabilize.
After the default oscillator has stabilized, oscillator calibration values are loaded from Non-Vola-
tile Memory into the Oscillator Calibration registers. Loading the calibration values takes 24
clock cycles on the internal 2 MHz oscillator. The 2 MHz, 32 MHz and 32 kHz internal RC oscil-
lators are calibrated. When this is done the device will enter active mode and program execution
will begin.
A Power-on detection circuit will give a Power-On Reset (POR) when supply voltage (V
applied to the device and the V
Power-on reset is released when the V
Power-on Threshold Voltage (V
When V
lower than the minimum operating voltage for the device, and is only used for power-off function-
SUT[1:0]
• Reset Counter Delay
• Oscillator startup
• Oscillator calibration
00
01
10
11
CC
is falling, the POR will issue a reset when the Vpot level is reached. The Vpot level is
Reset Counter Delay
POT
Number of 1 kHz ULP oscillator clock cycles
CC
) level.
slope is increasing in the Power-on Slope Range (V
CC
stops rising or when the V
Reserved
64
4
0
CC
level has reached the
XMEGA A
Table 9-
POSR
CC
104
) is
).