ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 350

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

29.4
29.4.1
29.4.2
29.4.3
29.4.3.1
8077H–AVR–12/09
JTAG Physical
Enabling
Disabling
JTAG Instruction Set
The PDICOM instruction
Figure 29-9. PDI direction change by inserting IDLE bits
The programmer will loose control of the PDI_DATA line at the point where the PDI target
changes from RX- to TX-mode. The Guard Time relaxes this critical phase of the communica-
tion. When the programmer changes from RX-mode to TX-mode, minimum a single IDLE bit
should be inserted before the start bit is transmitted.
The JTAG physical layer handles the basic low-level serial communication over four I/O lines;
TMS, TCK, TDI, and TDO. The JTAG physical layer includes BREAK detection, parity error
detection, and parity generation. For more details refer to
interface” on page
The JTAGEN Fuse must be programmed and the JTAG Disable bit in the MCU Control Register
must be cleared to enable the JTAG Interface. By default the JTAGEN fuse is programmed, and
the JTAG interface is enabled. When the JTAG instruction PDICOM is shifted into the JTAG
instruction register, the PDI communication register is chosen as the data register connected
between TDI and TDO. In this mode, the JTAG interface can be used to access the PDI for
external programming and on-chip debug.
The JTAG interface can be disabled by either unprogramming the JTAGEN fuse or by setting
the JTAG Disable bit in the MCU Control Register from the application code
The XMEGA JTAG Instruction set consist of eight instructions related to Boundary Scan and PDI
access for NVM programming, for details on the instruction set refer to
page
The 9-bit PDI communication register is selected as data register. Commands are shifted into
the register, while results from previous commands are shifted out from the register. The active
TAP-controller states are:
• Capture-DR: Parallel data from the PDI Controller is sampled into the PDI communication
• Shift-DR: The PDI communication register is shifted by the TCK input.
• Update-DR: Commands or operands are parallel-latched into registers in the PDI Controller.
register.
339.
St
d2W DATA Receive (RX)
337.
1 DATA character
Emulator to d2W
Data from
interface
P
Sp1
Sp2
IDLE bits
Dir. change
Guard time
# IDLE bits
inserted
St
”IEEE 1149.1 JTAG Boundary Scan
d2W DATA Transmit (TX)
1 DATA character
d2W interface
to Emulator
Data from
”JTAG instructions” on
XMEGA A
V
Sp1 Sp2
350