ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 298

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

25.9.3
25.9.4
8077H–AVR–12/09
Single conversions on two ADC channels
Single conversions on two ADC channels, CH0 with gain
Figure 25-14. ADC timing for one single conversion with gain
Figure 25-15 on page 298
The pipelined design enables the second conversion to start on the next ADC clock cycle after t
the first conversion is started. In this example both conversions is triggered at the same time, but
for ADC Channel 1 (CH1) the actual start is not until the ADC sample and conversion of the MSB
for ADC Channel 0 (CH0) is done.
Figure 25-15. ADC timing for single conversions on two ADC channels
Figure 25-16 on page 299
nels where ADC Channel 0 uses the gain stage. As the gain stage introduce one addition cycle
for the gain sample and amplify, the sample for ADC Channel 1 is also delayed one ADC clock
cycle, until the ADC sample and MSB conversion is done for ADC Channel 0.
CONVERTING BIT CH0
CONVERTING BIT CH1
GAINSTAGE AMPLIFY
GAINSTAGE SAMPLE
CONVERTING BIT
ADC SAMPLE
ADC SAMPLE
START CH0
START CH1
CLK
CLK
IF CH0
IF CH1
START
ADC
ADC
IF
1
1
MSB
shows the conversion timing for single conversions on two ADC chan-
10
shows the ADC timing for single conversions on two ADC channels.
2
2
MSB
MSB
9
10
10
8
3
3
9
7
9
8
6
8
4
4
7
5
7
6
4
6
5
5
5
3
5
4
2
4
6
6
3
1
3
LSB
2
2
7
7
1
1
XMEGA A
LSB
LSB
8
8
9
9
298