ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 220

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

19.9.4
8077H–AVR–12/09
STATUS - Master Status Register
• Bit 7 - RIF: Read Interrupt Flag
This Read Interrupt Flag (RIF) is set when a byte is successfully received in Master Read mode,
i.e. no arbitration lost or bus error occurred during the operation. Writing a one to this bit location
will clear the RIF. When this flag is set the master forces the SCL line low, stretching the TWI
clock period. Clearing the interrupt flags will release the SCL line.
This flag is also automatically cleared when:
• Bit 6 - WIF: Write Interrupt Flag
The Write Interrupt Flag (WIF) flag is set when a byte is transmitted in Master Write mode. The
flag is set regardless of the occurrence of a bus error or an arbitration lost condition. The WIF is
also set if arbitration is lost during sending of NACK in Master Read mode, and if issuing a
START condition when the bus state is unknown. Writing a one to this bit location will clear the
WIF. When this flag is set the master forces the SCL line low, stretching the TWI clock period.
Clearing the interrupt flags will release the SCL line.
The flag is also automatically cleared for the same conditions as RIF.
• Bit 5 - CLKHOLD: Clock Hold
The master Clock Hold (CLKHOLD) flag is set when the master is holding the SCL line low. This
is a status flag, and a read only bit that is set when the RIF and WIF is set. Clearing the interrupt
flags and releasing the SCL line, will indirectly clear this flag.
The flag is also automatically cleared for the same conditions as RIF.
• Bit 4 - RXACK: Received Acknowledge
The Received Acknowledge (RXACK) flag contains the most recently received acknowledge bit
from slave. This is a read only flag. When read as zero the most recent acknowledge bit from the
slave was ACK, and when read as one the most recent acknowledge bit was NACK.
• Bit 3 - ARBLOST: Arbitration Lost
The Arbitration Lost (ARBLOST) flag is set if arbitration is lost while transmitting a high data bit,
a NACK bit, or while issuing a START or Repeated START condition on the bus. Writing a one
to this bit location will clear the ARBLOST flag.
Writing the ADDR register will automatically clear the ARBLOST flag.
Bit
+0x03
Read/Write
Initial Value
• Writing to the ADDR register.
• Writing to the DATA register.
• Reading the DATA register.
• Writing a valid command to the CMD bits in the CTRLC register.
R/W
RIF
7
0
WIF
R/W
6
0
CLKHOLD
R/W
5
0
RXACK
R/W
4
0
ARBLOST
R/W
3
0
BUSERR
R/W
2
0
R/W
1
0
BUSSTATE[1:0]
XMEGA A
R/W
0
0
STATUS
220