ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 58

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

5.14.4
8077H–AVR–12/09
TRIGSRC - DMA Channel Trigger Source
Table 5-6.
• Bit 1:0 - DESTDIR[1:0]: DMA Channel Destination Address Mode
These bits decide the DMA channel destination address mode according to
58. These bits can not be changed if the channel is busy.
Table 5-7.
• Bit 7:0 - TRIGSRC[7:0]: DMA Channel Trigger Source Select
These bits select which trigger source is used for triggering a transfer on the DMA channel. A
zero value means that the trigger source is disabled. For each trigger source the value to put in
the TRIGSRC register is the sum of the module or peripheral’s base value, and the offset value
for the trigger source in the module or peripherals.
for all module and peripherals.
value for the trigger sources in the different modules and peripheral types. For modules or
peripherals which does not exist for a device, the transfer trigger does not exist. Refer to the
device data sheet for the list of peripherals available.
Bit
+0x03
Read/Write
Initial Value
DESTRELOAD[1:0]
DESTDIR[1:0]
00
01
10
11
00
01
10
11
R/W
DMA channel destination address reload settings
DMA channel destination address mode settings
7
0
Group Configuration
Group Configuration
R/W
6
0
TRANSACTION
BLOCK
BURST
NONE
FIXED
DEC
Table 5-9 on page 59
INC
R/W
-
5
0
R/W
4
0
TRIGSRC[7:0]
Description
Fixed
Increment
Decrement
Reserved
Description
No reload performed.
DMA channel destination address register is reloaded
with initial value at end of each block transfer.
DMA channel destination address register is reloaded
with initial value at end of each burst transfer.
DMA channel destination address register is reloaded
with initial value at end of each transaction.
R/W
Table 5-8 on page 59
3
0
to
Table 5-12 on page 60
R/W
2
0
R/W
1
0
shows the base value
XMEGA A
Table 5-7 on page
R/W
shows the offset
0
0
TRIGSRC
58