ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 219

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

19.9.3
8077H–AVR–12/09
CTRLC - TWI Master Control Register C
• Bits 7:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 - ACKACT: Acknowledge Action
The Acknowledge Action (ACKACT) bit defines the master's acknowledge behavior in Master
Read mode. The Acknowledge Action is executed when a command is written to the CMD bits. If
SMEN in Control Register B is set, the Acknowledge Action is performed when the DATA regis-
ter is read.
Table 19-3
Table 19-3.
• Bit 1:0 - CMD[1:0]: Command
Writing the Command (CMD) bits triggers a master operation as defined by
CMD bits are strobe bits, and always read as zero. The Acknowledge Action is only valid in Mas-
ter Read mode (R). In Master Write mode (W), a command will only result in a Repeated START
or STOP condition. The ACKACT bit and the CMD bits can be written at the same time, and then
the Acknowledge Action will be updated before the command is triggered.
Table 19-4.
Writing a command to the CMD bits will clear the master interrupt flags and the CLKHOLD flag.
Bit
+0x02
Read/Write
Initial Value
CMD[1:0]
00
01
10
11
ACKACT
lists the acknowledge actions.
0
1
7
R
0
-
ACKACT Bit Description
CMD Bit Description
R
6
0
MODE
-
W
R
X
X
X
Action
Send ACK
Send NACK
R
5
0
-
Operation
Reserved
Execute Acknowledge Action succeeded by repeated START
condition
No operation
Execute Acknowledge Action succeeded by a byte receive
Execute Acknowledge Action succeeded by issuing a STOP
condition
R
4
0
-
R
3
0
-
ACKACT
R/W
2
0
R/W
1
0
CMD[1:0]
XMEGA A
Table
R/W
0
0
19-4. The
CTRLC
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