ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 141

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

13.14.10 INTCTRL - Interrupt Control Register
13.14.11 INT0MASK - Interrupt 0 Mask Register
13.14.12 INT1MASK - Interrupt 1 Mask Register
8077H–AVR–12/09
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2/1:0 - INTnLVL[1:0]: Interrupt n Level
These bits enable interrupt request for port interrupt n and select the interrupt level as described
in
• Bit 7:0 - INT0MSK[7:0]: Interrupt 0 Mask Register
These bits are used to mask which pins can be used as sources for port interrupt 0. If
INT0MASKn is written to one, pin n is used as source for port interrupt 0.The input sense config-
uration for each pin is decided by the PINnCTRL-registers.
• Bit 7:0 - INT1MASK[7:0]: Interrupt 1 Mask Register
These bits are used to mask which pins can be used as sources for port interrupt 1. If
INT1MASKn is written to one, pin n is used as source for port interrupt 1.The input sense config-
uration for each pin is decided by the PINnCTRL-registers.
Bit
+0x09
Read/Write
Initial Value
Bit
+0x0B
Read/Write
Initial Value
Bit
+0x0A
Read/Write
Initial Value
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
R/W
R/W
7
R
0
7
0
-
7
0
R/W
R/W
6
R
0
6
0
-
6
0
R/W
R/W
R
5
0
5
0
-
5
0
R/W
R/W
R
4
0
4
0
-
4
0
INT1MSK[7:0]
INT0MSK[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
INT1LVL[1:0]
R/W
R/W
R/W
2
0
0
2
0
2
R/W
R/W
R/W
1
0
1
0
1
0
INT0LVL[1:0]
XMEGA A
R/W
R/W
R/W
0
0
0
0
0
0
123.
INT0MASK
INT1MASK
INTCTRL
141