ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 337

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

28. IEEE 1149.1 JTAG Boundary Scan interface
28.1
28.2
8077H–AVR–12/09
Features
Overview
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The JTAG Boundary-scan interface is mainly intended for testing PCBs by using the JTAG
Boundary-scan capability. Secondary, the JTAG interface is reused to access the Program and
Debug Interface (PDI) in its optional JTAG mode.
The Boundary-scan chain has the capability of driving and observing the logic levels on I/O pins.
At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals
to form a long shift register. An external controller sets up the devices to drive values at their out-
put pins, and observe the input values received from other devices. The controller compares the
received data with the expected result. In this way, Boundary-scan provides a mechanism for
testing interconnections and integrity of components on Printed Circuit Boards by using the four
TAP signals only.
The IEEE 1149.1-2001 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/
PRELOAD, and EXTEST together with the optional CLAMP, and HIGHZ instructions can be
used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the
ID-Code of the device, since IDCODE is the default JTAG instruction. If needed, the BYPASS
instruction can be issued to make the shortest possible scan chain through the device. The
EXTEST instruction is used for sampling external pins and loading output pins with data. The
data from the output latch will be driven out on the pins as soon as the EXTEST instruction is
loaded into the JTAG IR-Register. Therefore to avoid damaging the board when issuing the
EXTEST instruction for the first time, the merged SAMPLE/PRELOAD should be used for setting
initial values to the scan ring. SAMPLE/PRELOAD is also used for taking a non-intrusive snap-
shot of the external pins during normal operation of the part. The CLAMP instruction allows
static pin values to be applied via the Boundary-scan registers while bypassing these registers in
the scan path, efficiently shortening the total length of the serial test path. Alternatively the
HIGHZ instruction can be used to place all I/O pins in an inactive drive state, while bypassing the
Boundary-scan register chain of the chip.
The AVR specific PDICOM instruction makes it possible to use the PDI data register as an inter-
face for accessing the PDI for programming and debugging. Note that the PDICOM instruction
has nothing to do with Boundary-scan testing, but represents an alternative way to access inter-
nal programming and debugging resources by using the JTAG interface. For more details on
PDI, programming and on-chip debug refer to
page
The JTAGEN Fuse must be programmed and the JTAGD bit in the MCUCR Register must be
cleared to enable the JTAG Interface and Test Access Port.
JTAG (IEEE std. 1149.1-2001 compliant) interface.
Boundary-scan capabilities according to the JTAG standard.
Full scan of all I/O pins.
Supports the mandatory SAMPLE, PRELOAD, EXTEST, and BYPASS instructions.
Supports the optional IDCODE, HIGHZ, and CLAMP instructions.
Supports the AVR specific PDICOM instruction for accessing the PDI for debugging and
programming in its optional JTAG mode.
344.
Section 29. ”Program and Debug Interface” on
XMEGA A
337