ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 69

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

6.5
6.6
6.7
6.7.1
8077H–AVR–12/09
Event Timing
Filtering
Quadrature Decoder
Quadrature Operation
An event normally lasts for one peripheral clock cycle, but some event sources, such as low
level on an I/O pin, will generate events continuously. Details on this are described in the
datasheet for each peripheral, but unless stated, an event lasts for one peripheral clock cycle
only.
It takes maximum two clock cycles from an event is generated until the event actions in other
peripherals is triggered. It takes one clock cycle from the event happens until it is registered by
the event routing network on the first positive clock edge. It takes an additional clock cycle to
route the event through the event channel to the event user.
Each event channel includes a digital filter. When this is enabled for an event channel, an event
must be sampled with the same value for configurable number of system clock cycles before it is
accepted. This is primarily intended for pin change events.
The Event System includes three Quadrature Decoders (QDECs). This enables the Event Sys-
tem to decode quadrature input on I/O pins, and send data events that a Timer/Counter can
decode to trigger the appropriate event action: count up, count down or index/reset.
on page 69
decoded, and how they can be generated. The QDECs and related features, control and status
register are available for event channel 0, 2 and 4.
Table 6-2.
A quadrature signal is characterized by having two square waves phase shifted 90 degrees rela-
tive to each other. Rotational movement can be measured by counting the edges of the two
waveforms. The phase relationship between the two square waves determines the direction of
rotation.
STROBE
0
0
1
1
summarizes which quadrature decoder data events are available, how they are
DATA
Quadrature Decoder Data Events
0
1
0
1
Data Event User
No Event
Index/Reset
Count Down
Count Up
Signaling Event User
No Event
Signaling Event
Signaling Event
No Event
XMEGA A
Table 6-2
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