ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 27

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

4.15.8
4.15.9
8077H–AVR–12/09
CTRLA - Non-Volatile Memory Control Register A
CTRLB - Non-Volatile Memory Control Register B
• Bit 7:1 - Reserved Bits
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - CMDEX: Non-Volatile Memory Command Execute
Setting this bit will execute the command in the CMD register. This bit is protected by the Config-
uration Change Protection (CCP) mechanism, refer to
Protection” on page 12
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3 - EEMAPEN: EEPROM Data Memory Mapping Enable
Setting this bit will enable Data Memory Mapping of the EEPROM section. The EEPROM can
then be accessed using Load and Store instructions.
• Bit 2 - FPRM: Flash Power Reduction Mode
Setting this bit will enable power saving for the flash memory. The section not being accessed
will be turned off like in sleep mode. If code is running from Application Section, the Boot Loader
Section will be turned off and vice versa. If access to the section that is turned off is required, the
CPU will be halted equally long to the start-up time from the Idle sleep mode.
• Bit 1 - EPRM: EEPROM Power Reduction Mode
Setting this bit will enable power saving for the EEPROM memory. The EEPROM will then be
powered down equal to entering sleep mode. If access is required, the bus master will be halted
equally long as the start-up time from Idle sleep mode.
• Bit 0 - SPMLOCK: SPM Locked
The SPM Locked bit can be written to prevent all further self-programming. The bit is cleared at
reset and cannot be cleared from software. This bit is protected by the Configuration Change
Protection (CCP) mechanism, refer to
12
Bit
+0x0B
Read/Write
Initial Value
Bit
+0x0C
Read/Write
Initial Value
for details on the CCP.
R
7
0
-
R
7
0
-
R
6
0
for details on the CCP.
-
R
6
0
-
R
5
0
-
R
5
0
-
R
4
0
-
Section 3.12 ”Configuration Change Protection” on page
EEMAPEN
R
4
0
-
R/W
3
0
R
3
0
-
FPRM
R/W
2
0
Section 3.12 ”Configuration Change
R
2
0
-
EPRM
R/W
1
0
R
1
0
-
SPMLOCK
XMEGA A
R/W
CMDEX
0
0
S
0
0
CTRLA
CTRLB
27