ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 379

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

30.12 External Programming
8077H–AVR–12/09
External Programming is the method for programming non volatile code and data into the device
from an external programmer or debugger. This can be done both in-system (In-System Pro-
gramming) or in mass production programming. The only restrictions on clock speed and voltage
is the maximum and minimum operating conditions for the device. Refer to the device data sheet
for details on this.
For external programming the device is accessed through the PDI and PDI Controller, using
either the JTAG or PDI physical connection. For details on PDI and JTAG and how to enable
and use the physical interface, refer to
remainder of this section assumes that the correct physical connection to the PDI is enabled.
Through the PDI, the external programmer access all NVM memories and NVM Controller using
the PDI Bus. Doing this all data and program memory spaces are mapped into the linear PDI
memory space.
for each memory space in the device.
Figure 30-4 on page 380
”Program and Debug Interface” on page
shows the PDI memory space and the base address
XMEGA A
344. The
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