ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 443

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8077H–AVR–12/09
28 IEEE 1149.1 JTAG Boundary Scan interface ..................................... 337
29 Program and Debug Interface ............................................................. 344
30 Memory Programming ......................................................................... 362
31 Peripheral Module Address Map ........................................................ 386
32 Instruction Set Summary .................................................................... 388
27.11
28.1
28.2
28.3
28.4
28.5
28.6
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
30.1
30.2
30.3
30.4
30.5
30.6
30.7
30.8
30.9
30.10
30.11
30.12
30.13
30.14
Interrupt vector Summary ..............................................................................336
Features ........................................................................................................337
Overview ........................................................................................................337
TAP - Test Access Port .................................................................................338
JTAG instructions ..........................................................................................339
Data registers ................................................................................................341
Boundary-scan chain .....................................................................................342
Features ........................................................................................................344
Overview ........................................................................................................344
PDI Physical ..................................................................................................345
JTAG Physical ...............................................................................................350
PDI Controller ................................................................................................353
Register Description - PDI Instruction and Addressing Registers .................357
Register Description - PDI Control and Status Register ................................359
Register Summary .........................................................................................361
Features ........................................................................................................362
Overview ........................................................................................................362
NVM Controller ..............................................................................................363
NVM Commands ...........................................................................................363
NVM Controller Busy .....................................................................................363
Flash and EEPROM Page Buffers ................................................................364
Flash and EEPROM Programming Sequences .............................................365
Protection of NVM .........................................................................................366
Preventing NVM Corruption ...........................................................................366
CRC Functionality ..........................................................................................366
Self-Programming and Boot Loader Support ................................................367
External Programming ...................................................................................379
Register Description ......................................................................................385
Register Summary .........................................................................................385
XMEGA A
x