ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 264

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

23.5
23.5.1
8077H–AVR–12/09
Register Description - AES
CTRL - AES Control Register
• Bit 7 - START: AES Start/Run
Setting this bit starts the encryption/decryption procedure, and this bit remains set while the
encryption/decryption is ongoing. Writing this bit to zero will stop/abort any ongoing encryp-
tion/decryption process. This bit is automatically cleared if the SRIF or the ERROR flag in
STATUS is set.
• Bit 6 - AUTO: AES Auto Start Trigger
Setting this bit enables the Auto Start mode. In Auto Start mode the START bit will trigger auto-
matically and start the encryption/decryption when the following conditions are met:
If not will the encryption/decryption be started with an incorrect Key.
• Bit 5 - RESET: AES Software Reset
Setting this bit will reset the AES Crypto Module to its initial status on the next positive edge of
the Peripheral Clock. All registers, pointers and memories in the module are set to their initial
value. When written to one, the bit stays high for one clock cycle before it is reset to zero by
hardware.
• Bit 4 - DECRYPT: AES Decryption / Direction
This bit sets the direction for the AES Crypto Module. Writing this bit to zero will set the module
in encryption mode. Writing one to this bit sets the module in decryption mode.
• Bit 3 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 2 - XOR: AES State XOR Load Enable
Setting this bit enables XOR data load to the State memory. When this bit is set the data loaded
to the State memory is bitwise XOR'ed with current data in the State memory. Writing this bit to
zero disables XOR load mode, thus new data written to the State memory overwrites the current
data in the State memory.
Bit
+0x00
Read/Write
Initial Value
• The AUTO bit is set before the State memory is loaded.
• All memory pointers (State read/write and Key read/write) are zero.
• State memory is fully loaded.
START
R/W
7
0
AUTO
R/W
6
0
RESET
R/W
5
0
DECRYPT
R/W
4
0
R
3
0
-
XOR
R/W
2
0
R
1
0
-
XMEGA A
R
0
0
-
CTRL
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