ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 377

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

Table 30-4.
30.11.5.1
30.11.5.2
30.11.5.3
8077H–AVR–12/09
CMD[6:0]
EEPROM Page buffer
EEPROM
0x00
0x33
0x36
0x32
0x34
0x35
0x30
0x06
Group Configuration
NO_OPERATION
LOAD_EEPROM_BUFFER
ERASE_EEPROM _BUFFER
ERASE_EEPROM_PAGE
WRITE_EEPROM_PAGE
ERASE_WRITE_EEPROM_PAGE
ERASE_EEPROM
READ_EEPROM
Load EEPROM Page Buffer
Erase EEPROM Page Buffer
EPPROM Page Erase
EEPROM Self-Programming Commands
Section 30.11.5.1 on page 377
algorithm for each EEPROM operation.
The Load EEPROM Page Buffer command is used to load one byte into the EEPROM page
buffer.
1.
2.
3.
Repeat 2-3 until for the arbitrary number of bytes to be loaded into the page buffer.
The Erase EEPROM Buffer command is used to erase the EEPROM page buffer.
The BUSY flag in the NVM STATUS register will be set until the operation is finished.
The Erase EEPROM Erase command is used to erase one EEPROM page.
1.
2.
3.
during self-programming.
The BUSY flag in the NVM STATUS register will be set until the operation is finished.
The Page Erase commands will only erase the locations that correspond with the loaded and
tagged locations in the EEPROM page buffer.
1. Load the NVM CMD register with the Erase EEPROM Buffer command.
2. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence
during self-programming.
Load the NVM CMD register with the Load EEPROM Page Buffer command
Load the NVM ADDR0 register with the address to write.
Load the NVM DATA0 register with the data to write. This will trigger the command.
Set up the NVM CMD register to Erase EEPROM Page command.
Load the NVM ADDRESS register with the EEPROM page to erase.
Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence
Description
No Operation
Load EEPROM Page Buffer
Erase EEPROM Page Buffer
Erase EEPROM Page
Write EEPROM Page
Erase & Write EEPROM Page
Erase EEPROM
Read EEPROM
through
DATA0
CMDEX
CMDEX
CMDEX
CMDEX
CMDEX
CMDEX
Trigger
-
Section 30.11.5.7 on page 378
CPU
Halted
N
N
N
N
N
N
N
-
Change
Protected
Y
Y
Y
Y
Y
Y
Y
-
Address
pointer
-
ADDR
-
ADDR
ADDR
ADDR
-
ADDR
explains in details the
XMEGA A
Data
register
DATA0
DATA0
-
-
-
-
-
-
NVM
Busy
N
Y
Y
Y
Y
Y
N
Y
-
377