ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 318

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

26.3
26.4
26.5
8077H–AVR–12/09
Starting a conversion
Output channels
DAC Output model
Figure 26-1. DAC overview
Conversions are either done when data is written to the data registers, or timed by an incoming
event.
If auto trigger mode is not selected, a new conversion is automatically started when there is a
new value in the DAC data register. When auto trigger mode is selected, the new conversion will
be started on an incoming event from the selected event channel if there is new data in the data
register which has not been converted.
Both application software and the DMA controller may write to the data registers.
The output from the DAC can either be continuous to one pin (Channel 0), or fed into two differ-
ent pins using a sample and hold circuitry (S/H). With S/H these two outputs can act
independently and create two different analog signals, different in both voltage and frequency.
The two S/H outputs have individual data and conversion control registers. The DAC output may
be used as input to other peripherals in XMEGA, such as the Analog Comparator or the Analog
to Digital Converter. It is the output directly from the DAC, not the S/H outputs, that is available
for these peripherals.
Each DAC output channel has a driver buffer with feedback ensures that the voltage on the DAC
output pin is equal to the DACs internal voltage until the DAC output reaches its saturation volt-
age.
DAC characteristics in the device data sheet.
CH0DATA
CH1DATA
Figure 26-2 on page 319
12
12
Int. 1.00 V
AREFA
AREFB
AVCC
12
shows the DAC output model, for details on R
REFSEL
TRIG
CTRL
DAC
DAC
ENABLE
Control and Driver
ADC
AC
Output
XMEGA A
channel
, refer to the
DAC CH0
DAC CH1
318