ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 118

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

11.4
11.5
11.6
8077H–AVR–12/09
Window Mode Operation
Watchdog Timer clock
Configuration Protection and Lock
In window mode operation the WDT uses two different timeout periods, a "closed" window time-
out period (TO
defines a duration from 8 ms to 8s where the WDT cannot be reset: if the WDT is reset in this
period the WDT will issue a system reset. The normal WDT timeout period, which is also 8 ms to
8s, defines the duration of the "open" period, in which the WDT can (and should) be reset. The
open period will always follow the closed period, so the total duration of the timeout period is the
sum of the closed window and the open window timeout periods. The default closed window tim-
eout period is controlled by fuses. The window mode operation is illustrated in
Figure 11-2. Window mode operation.
The WDT is clocked from the 1 kHz output from the internal 32 kHz Ultra Low Power (ULP) oscil-
lator. Due to the ultra low power design, the oscillator is not very accurate so the exact timeout
period may vary from device to device. When designing software which uses the WDT, this
device-to-device variation must be kept in mind to ensure that the timeout periods used are valid
for all devices. For more information on the ULP oscillator accuracy, consult the device data
sheet.
The WDT is designed with two security mechanisms to avoid unintentional changes of the WDT
settings.
The first mechanism is the Configuration Change Protection mechanism, employing a timed
write procedure for changing the WDT control registers. In addition, for the new configuration to
be written to the control registers, the register’s Change Enable bit must be written at the same
time.
The second mechanism is to lock the configuration by setting the WDT lock fuse. When this fuse
is set, the Watchdog Time Control Register can not be changed, hence the WDT can not be dis-
abled from software. After system reset the WDT will resume at configured operation. When the
WDT lock fuse is programmed the window mode timeout period cannot be changed, but the win-
dow mode itself can still be enabled or disabled.
TO
TO
WDTW
WDT
WDTW
= 8
= 8
WDT Count
) and the normal timeout period (TO
5
10
15
TO
WDTW
20
TO
25
WDT
WDT
). The closed window timeout period
30
Timely WDT
Reset
35
Early WDT Reset
t [ms]
System Reset
XMEGA A
Figure
11-2.
118