ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 135

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

13.7
8077H–AVR–12/09
Port Interrupt
Each port has two interrupt vectors, and it is configurable which pins on the port that can be
used to trigger each interrupt request. Port interrupts must be enabled before they can be used.
Which sense configurations that can be used to generate interrupts is dependent on whether
synchronous or asynchronous input sensing is used.
For synchronous sensing, all sense configurations can be used to generate interrupts. For edge
detection, the changed pin value must be sampled once by the peripheral clock for an interrupt
request to be generated.
For asynchronous sensing, only port pin 2 on each port has full asynchronous sense support.
This means that for edge detection, pin 2 will detect and latch any edge and it will always trigger
an interrupt request. The other port pins have limited asynchronous sense support. This means
that for edge detection the changed value must be held until the device wakes up and a clock is
present. If the pin value returns to its initial value before the end of the device start-up time, the
device will still wake up, but no interrupt request will be generated.
A low level can always be detected by all pins, regardless of a peripheral clock being present or
not. If a pin is configured for low level sensing, the interrupt will trigger as long as the pin is held
low. In active mode the low level must be kept until the completion of the currently executing
instructions for an interrupt to be generated. In all sleep modes the low level must be kept until
the end of the device start-up time for an interrupt to be generated. If the low level disappears
before the end of the start-up time, the device will still wake up, but no interrupt will be
generated.
Table
gered for the various input sense configurations.
Table 13-1.
Table 13-2.
Sense settings
Rising edge
Falling edge
Both edges
Low level
Sense settings
Rising edge
Falling edge
Both edges
Low level
13-1,
Table
Synchronous sense support
Full asynchronous sense support
13-2, and
Table 13-3 on page 136
Supported
Supported
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt description
Always Triggered
Always Triggered
Always Triggered
Pin-level must be kept unchanged.
Interrupt description
Always Triggered
Always Triggered
Always Triggered
Pin-level must be kept unchanged.
summarizes when interrupts can be trig-
XMEGA A
135