ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 213

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

19.5
Figure 19-12. TWI Master Operation
8077H–AVR–12/09
SW
APPLICATION
TWI Master Operation
M1
Mn
SW
BUSY
Wait for
IDLE
Driver software
The master provides data
on the bus
Slave provides data on
the bus
Bus state
Diagram connections
M2
P
If a START condition is generated internally while in idle state the owner state is entered. If the
complete transaction was performed without interference, i.e. no collisions are detected, the
master will issue a STOP condition and the bus state changes back to idle. If a collision is
detected the arbitration is assumed lost and the bus state becomes busy until a STOP condition
is detected. A Repeated START condition will only change the bus state if arbitration is lost dur-
ing the issuing of the Repeated START.
The TWI master is byte-oriented with optional interrupt after each byte. There are separate inter-
rupts for Master Write and Master Read. Interrupt flags can also be used for polled operation.
There are dedicated status flags for indicating ACK/NACK received, bus error, arbitration lost,
clock hold and bus state.
When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond
or handle any data, and will in most cases require software interaction.
TWI master operation. The diamond shaped symbols (SW) indicate where software interaction
is required. Clearing the interrupt flags, releases the SCL line.
The number of interrupts generated is kept at a minimum by automatic handling of most condi-
tions. Quick Command and Smart Mode can be enabled to auto trigger operations and reduce
software complexity.
IDLE
M3
S
ADDRESS
R/W
R/W
W
R
BUSY
A
A
A
M4
MASTER WRITE INTERRUPT + HOLD
MASTER READ INTERRUPT + HOLD
SW
SW
SW
SW
SW
A/A
A/A
A/A
A
BUSY
BUSY
Sr
Sr
P
P
IDLE
IDLE
DATA
M1
M2
M3
M4
M2
M3
Figure 19-12
DATA
XMEGA A
A/A
BUSY
shows the
M4
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