ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 160

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

14.8.1
14.8.2
14.8.3
8077H–AVR–12/09
Waveform Generation
Frequency (FRQ) Waveform Generation
Single Slope PWM Generation
The compare channels can be used for waveform generation on the corresponding port pins. To
make the waveform visible on the connected port pin, the following requirements must be
fulfilled:
Inverted waveform output can be achieved by setting the invert output bit for the port pin.
For frequency generation the period time (T) is controlled by the CCA register instead of PER,
which in this case is not in use. The Waveform Generation (WG) output is toggled on each com-
pare match between the CNT and CCA registers as shown in
Figure 14-12. Frequency Waveform Generation
The waveform generated will have a maximum frequency of half of the Peripheral clock fre-
quency (f
Extension since this only increase the resolution and not the frequency. The waveform fre-
quency (f
where N represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n).
For single slope PWM generation, the Period (T) is controlled by the PER, while CCx registers
control the duty cycle of the WG output.
TOM to TOP then restarts from BOTTOM. The waveform generator (WG) output is set on the
compare match between the CNT and CCx registers, and cleared at TOP.
f
FRQ
1. A waveform generation mode must be selected.
2. Event actions must be disabled.
3. The CC channels to be used must be enabled. This will override the corresponding port
4. The direction for the associated port pin must be set to output.
CNT
WG Output
=
pin output register.
------------------------------- -
2N CCA+1
FRQ
PER
(
f
PER
MAX
BOT
TOP
)is defined by the following equation:
) when CCA is set to zero (0x0000). This also applies when using the Hi-Res
)
Period (T)
Figure 14-13
Direction Change
shows how the counter counts from BOT-
Figure 14-12 on page
CNT written
XMEGA A
"update"
160.
160