ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 185

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

15.7.6
15.7.7
15.7.8
15.7.9
8077H–AVR–12/09
DTBOTHBUF - Dead-time Concurrent Write to Both Sides Buffer
DTLS - Dead-Time Low Side Register
DTHS - Dead-Time High Side Register
DTLSBUF - Dead-Time Low Side Buffer Register
• Bit 7:0 - DTBOTH: Dead-Time Both Sides
Writing to this register will update both DTHS and DTLS registers at the same time (i.e. at the
same I/O write access).
• Bit 7:0 - DTBOTHBUF: Dead-Time Both Sides Buffer
Writing to this memory location will update both DTHSBUF and DTLSBUF registers at the same
time (i.e. at the same I/O write access).
• Bit 7:0 - DTLS: Dead-Time Low Side
This register holds the number of peripheral clock cycles for the Dead-Time Low Side.
• Bit 7:0 - DTHS: Dead-Time High Side
This register holds the number of peripheral clock cycles for the Dead-Time High Side.
• Bit 7:0 - DTLSBUF: Dead-Time Low Side Buffer
This register is the buffer for the DTLS Register. If double buffering is used, valid contents in this
register is copied to the DTLS Register on an UPDATE condition.
Bit
+0x07
Read/Write
Initial Value
Bit
+0x0A
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
DTBOTHBUF[7:0]
R/W
R/W
4
0
R/W
4
0
4
0
4
0
DTLSBUF[7:0]
DTHS[7:0]
DTLS[7:0]
R/W
3
0
R/W
R/W
R/W
3
0
3
0
3
0
R/W
2
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
1
0
R/W
R/W
R/W
1
0
1
0
1
0
XMEGA A
R/W
0
0
R/W
R/W
R/W
0
0
0
0
0
0
DTBOTHBUF
DTLSBUF
DTHS
DTLS
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