ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 161

MCU AVR 256KB FLASH A3B 64-QFN

ATXMEGA256A3B-MH

Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheets

Specifications of ATXMEGA256A3B-MH

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
14.8.4
8077H–AVR–12/09
Dual Slope PWM
Figure 14-13. Single slope Pulse Width Modulation
The PER register defines the PWM resolution. The minimum resolution is 2-bit (PER=0x0003),
and maximum resolution is 16-bit (PER=MAX).
The following equation can be used for calculate the exact resolution for single-slope PWM
(R
The single slow PWM frequency (f
eral clock frequency (f
where N represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n).
For dual slope PWM generation, the Period (T) is controlled by the PER, while CCx registers
control the duty cycle of the WG output.
ter counts repeatedly from BOTTOM to TOP, and then from TOP to BOTTOM. The waveform
generator output is set on BOTTOM, cleared on compare match when upcounting and set on
compare match when down counting.
R
f
PWM_SS
PWM_SS
PWM_SS
CNT
WG Output
=
):
=
------------------------------ -
N PER
log
---------------------------------- -
(
f
(
log
PER
MAX
PER
TOP
BOT
2 ( )
+
CCx
1
+
)
1
PER
)
), and can be calculated by the following equation:
Period (T)
PWM_SS
Figure 14-14
) depends on the period setting (PER) and the Periph-
CCx=BOT
shows how for dual slope PWM the Coun-
CCx=TOP
XMEGA A
"update"
"match"
161

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