ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 15

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

3.14.6
3.14.7
8077H–AVR–12/09
EIND - Extended Indirect Register
SPL - Stack Pointer Register Low
first 64K bytes, and writing (SPM) program memory locations above the first 128K bytes of the
program memory.
When accessing data addressees below 64K bytes, reading program memory locations below
64K bytes and writing program memory locations below 128K bytes, this register is not in use.
This register is not available if the data memory including external memory and program mem-
ory in the device is less than 64K bytes.
• Bit 7:0 – RAMPZ[7:0]: Extended Z-pointer Address bits
These bits holds the 8 MSB of the 24-bit address created by RAMPZ and the 16-bit Z-register.
Only the number of bits required to address the available data and program memory is imple-
mented for each device. Unused bits will always read as zero.
This register is concatenated with the Z-register for enabling extended indirect jump (EIJMP)
and call (ECALL) to the whole program memory space devices with more than 128K bytes of
program memory. For jump or call to addressees below 128K bytes, this register is not in use.
This register is not available if the program memory in the device is less than 128K bytes.
• Bit 7:0 - EIND[7:0]: Extended Indirect Address bits
These bits holds the 8 MSB of the 24-bit address created by EIND and the 16-bit Z-register.
Only the number of bits required to access the available program memory is implemented for
each device. Unused bits will always read as zero.
The SPH and SPL register pair represent the 16-bit value SP. The SP holds the Stack Pointer
that point to the top of the Stack. After reset, the Stack Pointer points to the highest internal
SRAM address.
Only the number of bits required to address the available data memory including external mem-
ory, up to 64K bytes is implemented for each device. Unused bits will always read as zero.
Note:
• Bit 7:0 - SP[7:0]: Stack Pointer Register Low byte
These bits hold the 8 LSB of the 16-bits Stack Pointer (SP).
Bit
+0x0B
Read/Write
Initial Value
Bit
+0x0D
Read/Write
Initial Value
Bit
+0x0C
Read/Write
Initial Value
(1)
1. Refer to specific device datasheets for exact initial values.
R/W
R/W
R/W
7
0
0/1
7
0
7
R/W
R/W
R/W
0/1
6
0
6
0
6
R/W
R/W
R/W
0/1
5
0
5
5
0
R/W
R/W
R/W
0/1
4
0
4
4
0
RAMPZ[7:0]
EIND[7:0]
SP[7:0]
R/W
R/W
R/W
0/1
3
3
0
3
0
R/W
R/W
R/W
0/1
2
2
0
2
0
R/W
0/1
R/W
R/W
1
1
0
1
0
XMEGA A
R/W
0/1
R/W
R/W
0
0
0
0
0
RAMPZ
EIND
SPL
15