ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 375

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

30.11.4
30.11.4.1
8077H–AVR–12/09
EEPROM Programming
Addressing the EEPROM
1.
2.
3.
during self-programming.
The result will be available in the NVM DATA0 register. The CPU is halted during the complete
execution of the command.
The EEPROM can be read and written from application code in any part of the Flash. Its is both
byte and page accessible. This means that either one byte or one page can be written to the
EEPROM at once. One byte is read from the EEPROM during read.
The EEPROM can be accessed through the NVM controller (I/O mapped), similar to the Flash
Program memory, or it can be memory mapped into the Data Memory space to be accessed
similar to SRAM.
When accessing the EEPROM through the NVM Controller, the NVM Address (ADDR) register
is used to address the EEPROM, while the NVM Data (DATA) register is used to store or load
EEPROM data.
For EEPROM page programming the ADDR register can be treated as having two section. The
least significant bits address the bytes within a page, while the most significant bits address the
page within the EEPROM. This is shown in
page (E2BYTE) is held by the bits [1:BYTEMSB] in the ADDR register. The remaining bits
[PAGEMSB:BYTEMSB+1] in the ADDR register holds the EEPROM page address (E2PAGE).
Together E2BYTE and E2PAGE holds an absolute address to a byte in the EEPROM. The size
of E2WORD and E2PAGE will depend on the page and flash size in the device, refer to the
device data sheet for details on this.
Load the NVM ADDR registers with the address to the fuse byte to read.
Load the NVM CMD register with the Read Fuses command.
Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence
Figure 30-3 on page
376. The byte address in the
XMEGA A
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