ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 269

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

24.3.2
24.3.3
24.4
8077H–AVR–12/09
I/O Pin Configuration
Address Size
Chip Select as Address Lines
The base address associated with each chip select must be on a 4 Kbyte boundary, i.e to
address 0, 4096, 8192 etc.
The address size selects how many bits of the address that should be compared when generat-
ing a chip select. The address size can be anything from 256 bytes to 16M bytes. If the address
space is set to anything larger than 4K bytes, the base address must be on a boundary equal to
the address space. With 1M byte address space for a chip select, the base address must be on
a 0, 1M byte, 2M byte etc. boundary.
If the EBI is configured so that if the address spaces overlap, the internal memory space have
priority, followed by Chip Select 0 (CS0), CS1, CS2 and CS3.
If one or more Chip Select lines are unused, they can in some combinations be used as address
lines instead. This can enable larger external memory or external CS generation. Each column
in
able on unused chip select lines (Ann). Column four shows that all four CS lines are used as
address lines when only CS3 is enabled, and this is for SDRAM configuring.
Figure 24-1. Chip Select and address line combinations
When the EBI is enabled it will override the direction and/or value for the I/O pins where the EBI
lines are placed. The EBI will override the direction and value for the I/O pins where the EBI data
lines are placed. The EBI will only override value, but not direction for the I/O pins where the EBI
address and control lines are placed. These I/O pins must be configured to output when the EBI
is used. I/O pins for unused EBI address and control lines can be used as normal I/O pins or for
other alternate functions on the pins.
For control signals that are active-low, the pin output value should be set to one (high). For con-
trol signals that are active-high, pin output value should be set to zero (low). Address lines does
not requires specific pin output value configuration. The Chip Select lines should have pull-up
resistors to ensure that these are kept high during power-on and reset. If a Chip Select line is
active-high, a pull-down should be used instead of a pull-up.
For more details on I/O pin configuration refer to
Figure 24-1 on page 269
shows enabled chip select lines (CSn), and the address lines avail-
CS3
CS2
CS1
CS0
CS3
CS2
CS1
A16
Section 13. on page
CS3
CS2
A17
A16
A19
A18
A17
A16
129.
XMEGA A
269