ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 61

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

5.14.6
5.14.7
5.14.8
8077H–AVR–12/09
TRFCNTL - DMA Channel Block Transfer Count Register L
REPCNT - DMA Channel Repeat Counter Register
SRCADDR2 - DMA Channel Source Address 2
• Bit 7:0 - TRFCNT[15:8]: DMA Channel n Block Transfer Count Register High byte
These bits hold the 8 MSB of the 16-bits block transfer count.
The default value of this register is 0x1. If a user write 0x0 to this register and fire a DMA trigger,
DMA will be doing 0xFFFF transfers.
• Bit 7:0 - TRFCNT[7:0]: DMA Channel n Block Transfer Count Register Low byte
These bits hold the 8 LSB of the 16-bits block transfer count.
The default value of this register is 0x1. If a user write 0x0 to this register and fire a DMA trigger,
DMA will be doing 0xFFFF transfers.
REPCNTcounts how many times a block transfer is performed. For each block transfer this reg-
ister will be decremented.
When repeat mode is enabled (see REPEAT bit in
trol Register” on page
counter is decremented after each block transfer if the DMA has to serve a limited number of
repeated block transfers. When repeat mode is enabled the channel is disabled when REPCNT
reaches zero, and the last block transfer is completed. Unlimited repeat is achieved by setting
this register to zero.
SRCADDR0, SRCADDR1 and SRCADDR2 represents the 24-bit value SRCADDR, which is the
DMA channel source address. SRCADDR2 is the most significant byte in the register.
SRCADDR may be automatically incremented or decremented based on settings in the SRCDIR
bits in
Reading and writing 24-bit values require special attention, for details refer to
”Accessing 24- and 32-bit Registers” on page
Bit
+0x06
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Bit
+0x0A
Read/Write
Initial Value
”ADDRCTRL - DMA Channel Address Control Register” on page
R/W
R/W
R/W
7
0
7
1
7
0
57), this register is used to control when the transaction is complete. The
R/W
R/W
R/W
6
0
6
1
6
0
R/W
R/W
R/W
5
0
5
1
5
0
R/W
R/W
R/W
SRCADDR[23:16]
4
0
4
1
4
0
TRFCNT[7:0]
REPCNT[7:0]
12.
R/W
R/W
R/W
”ADDRCTRL - DMA Channel Address Con-
3
1
3
0
3
0
R/W
R/W
R/W
2
0
2
1
2
0
R/W
R/W
R/W
1
1
1
0
1
0
57.
XMEGA A
R/W
R/W
R/W
0
1
0
0
0
0
Section 3.11.1
SRCADDR2
TRFCNTL
REPCNT
61