ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 192

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

17.3.2
17.3.3
8077H–AVR–12/09
STATUS - Real Time Counter Status Register
INTCTRL - Real Time Counter Interrupt Control Register
• Bits 7:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - SYNCBUSY: RTC Synchronization Busy Flag
This bit is set when the CNT, CTRL, PER or COMP register is busy synchronizing between the
RTC clock and system clock domains.
• Bits 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 3:2 - COMPINTLVL[1:0]: RTC Compare Match Interrupt Enable
These bits enable the RTC Compare Match Interrupt and select the interrupt level as described
in
enabled interrupt will trigger when the COMPIF in the INTFLAGS register is set.
• Bits 1:0 - OVFINTLVL[1:0]: RTC Overflow Interrupt Enable
These bits enable the RTC Overflow Interrupt and select the interrupt level as described in
tion 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
interrupt will trigger when the OVFIF in the INTFLAGS register is set.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
7
R
0
-
7
R
0
-
R
6
0
-
6
R
0
-
R
5
0
-
R
5
0
-
R
4
0
-
R
4
0
-
R/W
R
3
0
COMPINTLVL[1:0]
-
3
0
R/W
R
2
0
-
2
0
R
R/W
1
0
-
1
OVFINTLVL[1:0]
0
XMEGA A
SYNCBUSY
123. The enabled
R/W
R/W
0
0
0
0
123. The
INTCTRL
STATUS
Sec-
192