ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 57

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

5.14.3
8077H–AVR–12/09
ADDRCTRL - DMA Channel Address Control Register
• Bit [3:2] - ERRINTLVL[1:0]: DMA Channel Error Interrupt Level
These bits enable the interrupt for DMA channel transfer error select the interrupt level as
described in
123. The enabled interrupt will trigger for the conditions when the ERRIF is set.
• Bit [1:0] - TRNINTLVL[1:0]: DMA Channel Transaction Complete Interrupt Level
These bits enable the interrupt for DMA channel transaction complete and select the interrupt
level as described in
on page
• Bit 7:6 - SRCRELOAD[1:0]: DMA Channel Source Address Reload
These bits decide the DMA channel source address reload according to
can not be changed if the channel is busy.
Table 5-4.
• Bit 5:4 - SRCDIR[1:0]: DMA Channel Source Address Mode
These bits decide the DMA channel source address mode according to
can not be changed if the channel is busy.
Table 5-5.
• Bit 3:2 - DESTRELOAD[1:0]: DMA Channel Destination Address Reload
These bits decide the DMA channel destination address reload according to
58. These bits can not be changed if the channel is busy.
Bit
+0x02
Read/Write
Initial Value
SRCRELOAD[1:0]
SRCDIR[1:0]
123. The enabled interrupt will trigger for the conditions when the TRNIF is set.
00
01
10
11
00
01
10
11
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
R/W
SRCRELOAD[1:0]
DMA channel source address reload settings
DMA channel source address mode settings
7
0
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller”
Group Configuration
R/W
Group Configuration
6
0
TRANSACTION
BLOCK
BURST
FIXED
NONE
DEC
INC
R/W
-
5
0
SRCDIR[1:0]
R/W
4
0
Description
Fixed
Increment
Decrement
Reserved
Description
No reload performed.
DMA source address register is reloaded with initial
value at end of each block transfer.
DMA source address register is reloaded with initial
value at end of each burst transfer.
DMA source address register is reloaded with initial
value at end of each transaction.
DESTRELOAD[1:0]
3
R
0
R/W
2
0
R/W
1
0
DESTDIR[1:0]
Table
Table
XMEGA A
Table 5-6 on page
R/W
5-5. These bits
0
0
5-4. These bits
ADDRCTRL
57