ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 215

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

19.6
Figure 19-13. TWI Slave Operation
19.6.1
8077H–AVR–12/09
S1
S2
SW
Sn
Driver software
The master provides data
on the bus
Slave provides data on
the bus
Diagram connections
TWI Slave Operation
Receiving Address Packets
S3
S
ADDRESS
since arbitration can be lost during the transmission. If a collision is detected the master looses
arbitration and the Arbitration Lost flag is set.
The TWI slave is byte-oriented with optional interrupts after each byte. There are separate slave
Data Interrupt and Address/Stop Interrupt. Interrupt flags can also be used for polled operation.
There are dedicated status flags for indicating ACK/NACK received, clock hold, collision, bus
error and read/write direction.
When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond
or handle any data, and will in most cases require software interaction.
TWI slave operation. The diamond shapes symbols (SW) indicate where software interaction is
required.
The number of interrupts generated is kept at a minimum by automatic handling of most condi-
tions. Quick Command can be enabled to auto trigger operations and reduce software
complexity.
Promiscuous Mode can be enabled to allow the slave to respond to all received addresses.
When the TWI slave is properly configured, it will wait for a START condition to be detected.
When this happens, the successive address byte will be received and checked by the address
match logic, and the slave will ACK the correct address. If the received address is not a match,
the slave will not acknowledge the address and wait for a new START condition.
The slave Address/Stop Interrupt Flag is set when a START condition succeeded by a valid
address packet is detected. A general call address will also set the interrupt flag.
A START condition immediately followed by a STOP condition, is an illegal operation and the
Bus Error flag is set.
Condition Enabled
Interrupt on STOP
SLAVE ADDRESS INTERRUPT
Collision
(SMBus)
W
R
SW
SW
SW
SW
Release
Hold
A/A
A
A
A
S1
S1
S1
Sr
P
S2
S3
DATA
SLAVE DATA INTERRUPT
SW
SW
A/A
Figure
Sr
P
XMEGA A
S2
S3
19-13. shows the
DATA
A/A
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