ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 299

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

25.9.5
25.9.6
8077H–AVR–12/09
Single conversions on two ADC channels, CH1 with gain
Free running mode on two ADC channels with gain
Figure 25-16. ADC timing for single conversion on two ADC channels, CH0 with gain
Figure 25-17 on page 299
nels where ADC Channel 1 uses the gain stage.
Figure 25-17. ADC timing for single conversion on two ADC channels, CH1 with gain
Figure 25-18 on page 300
mode, CH0 and CH1 without gain and CH2 and CH3 with gain. When set up in free running
mode a ADC channel will continuously sample and do new conversions. In this example all ADC
channels are triggered at the same time, and each ADC channel sample and start converting as
soon as the previous ADC channel is done with it sample and MSB conversion. After four ADC
clock cycles all ADC channels have done the first sample and started the first conversion, and
each ADC channels can then do the sample conversion start for the second conversions. After 8
(for 12-bit mode) ADC clock cycles the first conversion is done for ADC Channel 0, and the
results for the rest of the ADC Channels is available in the next ADC clock cycles. After the next
clock cycle (in cycle 10) the result from the second ADC Channel is done and available and so
on. In this mode up to 8 conversions are ongoing at the same time.
CONVERTING BIT CH0
CONVERTING BIT CH1
CONVERTING BIT CH0
CONVERTING BIT CH1
GAINSTAGE AMPLIFY
GAINSTAGE AMPLIFY
GAINSTAGE SAMPLE
GAINSTAGE SAMPLE
START CH1, wo/GAIN
START CH0, wo/GAIN
START CH0, w/GAIN
START CH1, w/GAIN
ADC SAMPLE
ADC SAMPLE
CLK
CLK
IF CH0
IF CH1
IF CH0
IF CH1
ADC
ADC
1
1
shows the conversion timing for single conversions on two ADC chan-
shows the conversion timing for all four ADC channels in free running
2
2
MSB
MSB
10
10
3
3
MSB
MSB
9
9
10
10
8
8
4
4
7
9
7
9
6
8
6
8
5
5
5
7
5
7
4
6
4
6
6
6
3
5
3
5
2
4
2
4
7
7
1
3
1
3
LSB
LSB
2
2
8
8
1
1
XMEGA A
LSB
LSB
9
9
10
10
299