ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 218

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

19.9.2
8077H–AVR–12/09
CTRLB - TWI Master Control Register B
• Bit 4 - WIEN: Write Interrupt Enable
Setting the Write Interrupt Enable (WIEN) bit enables the Write Interrupt when the Write Interrupt
Flag (WIF) in the STATUS register is set. In addition the INTLVL bits must be unequal zero for
TWI master interrupts to be generated.
• Bit 3 - ENABLE: Enable TWI Master
Setting the Enable TWI Master (ENABLE) bit enables the TWI Master.
• Bit 2:0 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 7:4 - Reserved Bits
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 - TIMEOUT[1:0]: Inactive Bus Timeout
Setting the Inactive Bus Timeout (TIMEOUT) bits unequal zero will enable the inactive bus time-
out supervisor. If the bus is inactive for longer than the TIMEOUT settings, the bus state logic
will enter the idle state.
Figure 19-2
Table 19-2.
• Bit 1 - QCEN: Quick Command Enable
Setting the Quick Command Enable (QCEN) bit enables Quick Command. When Quick Com-
mand is enabled, a STOP condition is sent immediate after the slave acknowledges the
address.
• Bit 0 - SMEN: Smart Mode Enable
Setting the Smart Mode Enable (SMEN) bit enables Smart Mode. When Smart mode is enabled,
the Acknowledge Action, as set by the ACKACT bit in Control Register C, is sent immediately
after reading the DATA register.
Bit
+0x01
Read/Write
Initial Value
TIMEOUT[1:0]
00
01
10
11
lists the timeout settings.
7
R
0
-
TWI master inactive bus timeout settings
Group Configuration
6
R
0
-
DISABLED
100US
200US
50US
R
5
0
-
R
4
0
-
Description
Disabled, normally used for I
50 µs, normally used for SMBus at 100 kHz
R/W
3
0
TIMEOUT[1:0]
R/W
2
0
100 µs
200 µs
QCEN
R/W
2
1
0
C
XMEGA A
SMEN
R/W
0
0
CTRLB
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