ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 51

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

5.5
5.6
5.7
5.8
8077H–AVR–12/09
Addressing
Priority Between Channels
Double Buffering
Transfer Buffers
By default, a trigger starts a block transfer operation. The transfer continues until one block is
transferred. When the block is transferred, the channel will wait for the next trigger to arrive
before it start transferring the next block. It is possible to select the trigger to start a burst transfer
instead of a block transfer. This is called a single shot transfer. A new trigger will then start a new
burst transfer. When repeat mode is enabled, the start of transfer of the next block does not
require a transfer trigger. It will start as soon as the previous block is done.
If the trigger source generates a transfer request during an ongoing transfer this will be kept
pending, and the transfer can start when the ongoing one is done. Only one pending transfer
can be kept, so if the trigger source generates more transfer requests when one is already pend-
ing, these will be lost.
The source and destination address for a DMA transfer can either be static, incremental or dec-
remental with individual selections for source and destination. When address increment or
decrement is used, the default behaviour is to update the address after each access. The origi-
nal source and destination address is stored by the DMA controller, so the source and
destination addresses can be individually configured to be reloaded at the following points:
If several channels request data transfer at the same time a priority scheme is available to deter-
mine which channel is allowed to transfer data. Application software can decide whether one or
more channels should have a fixed priority or if a round robin scheme should be used. A round
robin scheme means that the channel that last transferred data will have the lowest priority.
To allow for continuous transfer, two channels can be interlinked so that the second takes over
the transfer when the first is finished and vice versa. This is called double buffering. When a
transmission is completed for the first channel, the second channel is enabled. When a request
is detected on the second channel, the transfer starts and when this is completed the first chan-
nel is enabled again.
Each DMA channel has an internal transfer buffer that is used for 2, 4 and 8 byte burst transfers.
When a transfer is triggered, a DMA channel will wait until the transfer buffer contains two bytes
before the transfer starts. For 4 or 8 byte transfer, any remaining bytes is transferred as soon as
they are ready for a DMA channel. The buffer is used to reduce the time the DMA controller
occupy the bus. When the DMA controller or a DMA channel is disabled from software, any
remaining bytes in the buffer will be transferred before the DMA controller or DMA channel is
disabled. This ensures that the source and destination address registers are kept synchronized.
• End of each burst transfer
• End of each block transfer
• End of transaction
• Never reload
XMEGA A
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