ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 323

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8077H–AVR–12/09
Table 26-4
for longer conversion intervals during dual channel operation, a 50% increase in the number
peripheral clock cycles is automatically added.
Table 26-4.
The number of clock cycles selected multiplied with the period of the Peripheral clock gives the
minimum DAC conversion internal.
• Bits 3:0 - REFRESH[3:0]: DAC Channel Refresh Timing Control
These bits control time interval between each time a channel is refreshed in dual channel (S/H)
mode. The interval must be set relative to the Peripheral clock to avoid loosing accuracy of the
converted value.
Table 26-5
Table 26-5.
CONINTCAL[2:0]
REFRESH[3:0]
000
001
010
011
100
101
110
111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
shows the available control settings as a number of peripheral clock cycles. To allow
shows the available timing control settings as a number of peripheral clock cycles.
DAC Conversion Interval
DAC Channel refresh control selection
Group Configuration
Group Configuration
128CLK
16CLK
32CLK
64CLK
1CLK
2CLK
4CLK
8CLK
16384CLK
32768CLK
65536CLK
1024CLK
2048CLK
4096CLK
8192CLK
128CLK
256CLK
512CLK
16CLK
32CLK
64CLK
clk
channel operation
PER
cycles for Single
128 CLK
16 CLK
32 CLK
64 CLK
1 CLK
2 CLK
4 CLK
8 CLK
clk
PER
cycles refresh interval
16384 CLK
32768 CLK
65536 CLK
1024 CLK
2048 CLK
4096 CLK
8192 CLK
128 CLK
256 CLK
512 CLK
16 CLK
32 CLK
64 CLK
channel (S/H) operation
clk
PER
XMEGA A
cycles for dual
192 CLK
12 CLK
24 CLK
48 CLK
96 CLK
1 CLK
3 CLK
6 CLK
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