ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 71

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

6.8
6.8.1
8077H–AVR–12/09
Register Description
CHnMUX – Event Channel n Multiplexer Register
The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read
directly from the Timer/Counter Count register. If the Count register is different from BOTTOM
when the index is recognized, the Timer/Counter error flag is set. Similarly the error flag is set if
the position counter passes BOTTOM without the recognition of the index.
.
• Bit 7:0 - CHnMUX[7:0]: Channel Multiplexer
These bits select the event source according to
devices regardless of if the peripheral is present or not. Selecting event sources from peripher-
als that are not present will give the same result as when this register is zero. When this register
is zero no events are routed through. Manually generated events will override the CHnMUX and
be routed to the event channel even if this register is zero.
Table 6-3.
Bit
Read/Write
Initial Value
• Set the period register of the Timer/Counter to ('line count' * 4 - 1). (The line count of the
• Enable the Timer/Counter by setting CLKSEL to a CLKSEL_DIV1.
CHnMUX[7:4]
quadrature encoder).
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0001
0001
0001
R/W
CHnMUX[7:0] Bit Settings
7
0
CHnMUX[3:0]
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
R/W
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
6
0
X
X
0
0
1
0
0
1
0
0
1
1
0
0
1
X
X
X
X
X
R/W
0
1
0
1
0
1
0
1
0
1
5
0
Group Configuration
RTC_OVF
RTC_CMP
ACA_CH0
ACA_CH1
ACA_WIN
ACB_CH0
ACB_CH1
ACB_WIN
R/W
4
0
CHnMUX[7:0]
Table
R/W
3
0
6-3. This table is valid for all XMEGA
R/W
Event Source
None (manually generated events
only)
(Reserved)
(Reserved)
(Reserved)
RTC Overflow
RTC Compare March
(Reserved)
(Reserved)
ACA Channel 0
ACA Channel 1
ACA Window
ACB Channel 0
ACB Channel 1
ACB Window
(Reserved)
2
0
R/W
1
0
XMEGA A
R/W
0
0
CHnMUX
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