ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 107

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

9.4.3
9.4.4
8077H–AVR–12/09
External reset
Watchdog reset
The BODACT fuse determines the BOD setting for active mode and idle mode, while the
BODPD fuse determines the brown-out detection setting for all sleep modes except idle mode.
Table 9-3.
The External reset circuit is connected to the external RESET pin. The external reset will trigger
when the RESET pin is driven below the RESET pin threshold voltage, V
minimum pulse period t
includes an internal pull-up resistor.
Figure 9-5.
For characterization data on V
sheet.
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. If the
WDT is not reset from the software within a programmable timout period, a Watchdog reset will
be given. The Watchdog reset is active for 1-2 clock cycles on the 2 MHz internal RC oscillator.
• Sampled: In this mode the BOD circuit will sample the VCC level with a period identical to
the 1 kHz output from the Ultra Low Power (ULP) oscillator. Between each sample the BOD is
turned off. This mode will reduce the power consumption compared to the enabled mode, but
a fall in the V
If a brown-out is detected in this mode, the BOD circuit is set in enabled mode to ensure that
the device is kept in reset until V
CC
BOD setting Fuse Decoding
External reset characteristics.
CC
level between 2 positive edges of the 1 kHz ULP output will not be detected.
BODACT[1:0]/ BODPD[1:0]
EXT
. The reset will be held as long as the pin is kept low. The reset pin
RST
00
01
10
11
and t
CC
is above V
EXT
and pull-up resistor values consult the device data
BOT
again.
RST
, for longer than the
XMEGA A
Reserved
Sampled
Disabled
Enabled
Mode
107