ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 128

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

12.8.3
12.9
8077H–AVR–12/09
Address
+0x00
+0x01
+0x02
Register Summary
CTRL - PMIC Control Register
Name
STATUS
INTPRI
CTRL
change the priority queue. This register is not reinitialized to its initial value if round-robing
scheduling is disabled, so if default static priority is needed the register must be written to zero.
• Bit 7 - RREN: Round-robin Scheduling Enable
When the RREN bit is set the round-robin scheduling scheme is enabled for low level interrupts.
When this bit is cleared, the priority is static according to interrupt vector address where the low-
est address has the highest priority.
• Bit 6 - IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Applica-
tion section in flash. When this bit is set (one), the interrupt vectors are moved to the beginning
of the Boot section of the Flash. Refer to the device data sheet for the absolute address.
This bit is protected by the Configuration Change Protection mechanism, refer to
”Configuration Change Protection” on page 12
• Bit 5:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 - HILVLEN: High Level Interrupt Enable
When this bit is set all high level interrupts are enabled. If this bit is cleared, high level interrupt
requests will be ignored.
• Bit 1 - MEDLVLEN: Medium Level Interrupt Enable
When this bit is set all medium level interrupts are enabled. If this bit is cleared, medium level
interrupt requests will be ignored.
• Bit 0 - LOLVLEN: Low Level Interrupt Enable
When this bit is set all low level interrupts are enabled. If this bit is cleared, low level interrupt
requests will be ignored.
NMIEX
Bit 7
Bit
+0x02
Read/Write
Initial Value
RREN
Bit 6
IVSEL
RREN
-
R/W
7
0
IVSEL
Bit 5
R/W
6
0
-
-
R
5
0
-
Bit 4
-
-
INTPRI[7:0]
R
4
0
-
Bit 3
-
-
for details.
R
3
0
-
HILVLEN
HILVLEX
Bit 2
HILVLEN
R/W
2
0
MEDLVLEN
MEDLVLEX
Bit 1
MEDLVLEN
R/W
1
0
LOLVLEN
LOLVLEX
XMEGA A
Bit 0
LOLVLEN
R/W
0
0
Section 3.12
Page
CTRL
127
127
128
128