ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 353

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

29.4.7
29.4.7.1
29.4.7.2
29.5
29.5.1
29.5.2
8077H–AVR–12/09
PDI Controller
Serial reception
Switching between PDI- and JTAG-mode
Accessing Internal Interfaces
Parity checker
BREAK detector
During reception, the receiver collects the eight data bits and the Parity bit from TDI and shifts
them into the shift register. Every time a valid frame is received, the data is latched in a parallel
way in the Update-DR state.
The Parity Checker calculates the parity (even mode) of the data bits in incoming frames and
compares the result with the parity bit from the serial frame. In case of a parity error, the PDI
Controller is signalized.
The Parity checker is active in both TX- and RX-mode. If a parity error is detected, the received
data byte is evaluated and compared with the BREAK character (which always will generate a
parity error). In case the BREAK character is recognized, the PDI Controller is signalized.
The PDI Controller includes data transmission/reception on a byte level, command decoding,
high-level direction control, control and status register access, exception handling, and clock
switching (PDI_CLK or TCK). The interaction between a programmer and the PDI Controller is
based on a scheme where the programmer transmits various types of requests to the PDI Con-
troller, which in turn responds in a way according to the specific request. A programmer request
comes in the form of an instruction, which may be followed by one or more byte operands. The
PDI Controller response may be silent (e.g. a data byte is stored to a location within the target),
or it may involve data to be returned back to the programmer (e.g. a data byte is read from a
location within the target).
The PDI Controller uses either the JTAG - or the PDI physical layer for establishing a connection
to the programmer. Based on this, the PDI is said to be in either JTAG or PDI mode. When one
of the modes are entered, the PDI Controller registers will be initialized, and the correct clock
source is selected by the clock system. It should be noted that the PDI mode has higher priority
than the JTAG mode. Hence, if the PDI mode is enabled while the PDI Controller is already in
JTAG mode, the access layer will automatically switch over to PDI mode. Still, if by some reason
a user wants to switch physical layer without power on/off the device, the active layer should be
disabled (to trigger a reset of the PDI) before the alternative physical layer is enabled.
After an external programmer has established communication with the PDI, the internal inter-
faces are not accessible by default. To get access to the NVM Controller and the NVM
memories for programming, a unique key must be signalized by using the KEY instruction. The
internal interfaces is accessed as one linear address space using a dedicated bus (PDIBUS)
between the PDI and the internal interfaces. The PDIBUS address space is the one shown in
Figure 30-4 on page
access to the NVMs. The PDI controller can only access the NVM and NVM controller in pro-
gramming mode. The PDI controller does not ever need to access the NVM controller's data or
address registers when reading or writing NVM.
380. The NVM controller must be enabled for the PDI controller to have any
XMEGA A
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