ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 97

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8.3.4
8.3.5
8.4
8.5
8.5.1
8077H–AVR–12/09
Power Reduction Registers
Register Description – Sleep
Standby Mode
Extended Standby Mode
CTRL- Sleep Control Register
Standby mode is identical to Power-down with the exception that the enabled system clock
sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces
the wake-up time.
Extended Standby mode is identical to Power-save mode with the exception that the enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time.
The Power Reduction (PR) registers provides a method to stop the clock to individual peripher-
als. When this is done the current state of the peripheral is frozen and the associated I/O
registers cannot be read or written. Resources used by the peripheral will remain occupied;
hence the peripheral should in most cases be disabled before stopping the clock. Enabling the
clock to a peripheral again, puts the peripheral in the same state as before it was stopped. This
can be used in Idle mode and Active mode to reduce the overall power consumption signifi-
cantly. In all other sleep modes, the peripheral clock is already stopped.
Not all devices have all the peripherals associated with a bit in the power reduction registers.
Setting a power reduction bit for a peripheral that is not available will have no effect.
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:1 - SMODE[2:0]: Sleep Mode Selection
These bits select sleep modes according to
Table 8-2.
Bit
+0x00
Read/Write
Initial Value
SMODE[2:0]
XXX
000
001
010
011
100
R
7
0
-
Sleep mode
R
6
0
-
SEN
0
1
1
1
1
1
R
5
0
-
R
4
0
-
Table 8-2 on page
Group Configuration
PDOWN
R/W
PSAVE
3
0
IDLE
OFF
-
-
SMODE[2:0]
R/W
2
0
97.
R/W
Description
No sleep mode enabled
Idle Mode
Reserved
Power-down Mode
Power-save Mode
Reserved
1
0
XMEGA A
SEN
R/W
0
0
CTRL
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