ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 357

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

29.6
29.6.1
29.6.2
8077H–AVR–12/09
Register Description - PDI Instruction and Addressing Registers
Instruction Register
Pointer Register
Figure 29-14. PDI instruction set summary
These registers are all internal registers that are involved in instruction decoding or PDIBUS
addressing. None of these registers are accessible as register in a register space.
When an instruction is successfully shifted into the physical layer shift-register, it is copied into
the Instruction Register. The instruction is retained until another instruction is loaded. The rea-
son for this is that the REPEAT command may force the same instruction to be run repeatedly
requiring command decoding to be performed several times on the same instruction.
The Pointer Register is used to store an address value specifying locations within the PDIBUS
address space. During direct data access, the Pointer Register is updated by the specified num-
ber of address bytes given as operand bytes to the instruction. During indirect data access,
addressing is based on an address already stored in the Pointer Register prior to the access
REPEAT
LDCS
STCS
LDS
STS
KEY
LD
ST
0
0
0
1
1
1
1
0
Cmd
Cmd
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
Size A
Ptr
CS Address
0
0
0
Size A/B
Size B
Size B
0
Cmd
0
0
0
0
1
1
1
1
Size A - Address size (direct access)
0
0
1
1 1
Ptr - Pointer access (indirect access)
0
0
1
1 1
Size B - Data size
0
0
1
1 1
CS Address (CS - Control/Status reg.)
0
0
0
0
1
0
0
1
1 1
0 0
0
1
1 1
0
1
0
0
1
0
0
1
0
0 0
0 0
0 1
0 1
1 1
0
1
0
1
0
Byte
Word (2 Bytes)
3 Bytes
Long (4 Bytes)
*(ptr)
*(ptr++)
ptr
ptr++ - Reserved
Byte
Word (2 Bytes)
3 Bytes
Long (4 Bytes)
LDS
LD
STS
ST
LDCS (LDS Control/Status)
REPEAT
STCS (STS Control/Status)
KEY
0
1
0
1
1
Register 0
Register 1
Register 2
Reserved
Reserved
......
XMEGA A
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