ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 439

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

8077H–AVR–12/09
16 Hi-Res - High Resolution Extension ................................................... 188
17 RTC - Real Time Counter ..................................................................... 190
18 RTC32 - 32-bit Real Time Counter ...................................................... 197
19 TWI – Two Wire Interface .................................................................... 205
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
16.1
16.2
16.3
16.4
17.1
17.2
17.3
17.4
17.5
18.1
18.2
18.3
18.4
18.5
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
Features ........................................................................................................176
Overview ........................................................................................................176
Port Override .................................................................................................177
Dead Time Insertion ......................................................................................179
Pattern Generation ........................................................................................180
Fault Protection .............................................................................................181
Register Description ......................................................................................182
Register Summary .........................................................................................187
Features ........................................................................................................188
Overview ........................................................................................................188
Register Description ......................................................................................189
Register Summary .........................................................................................189
Features ........................................................................................................190
Overview ........................................................................................................190
Register Description ......................................................................................191
Register Summary .........................................................................................196
Interrupt Vector Summary .............................................................................196
Features ........................................................................................................197
Overview ........................................................................................................197
Register Description ......................................................................................198
Register Summary .........................................................................................204
Interrupt Vector Summary .............................................................................204
Features ........................................................................................................205
Overview ........................................................................................................205
General TWI Bus Concepts ...........................................................................206
TWI Bus State Logic ......................................................................................212
TWI Master Operation ...................................................................................213
TWI Slave Operation .....................................................................................215
Enabling External Driver Interface .................................................................216
Register Description - TWI ............................................................................217
Register Description - TWI Master ................................................................217
XMEGA A
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