ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 117

• Manufacturer Part Number: ATXMEGA256A3B-MH
• Description: MCU AVR 256KB FLASH A3B 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA256A3B-MU; ATXMEGA256A3B-MU

11. WDT – Watchdog Timer
11.1
11.2
11.3
8077H–AVR–12/09
Features
Overview
Normal Mode Operation
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•
•
•
The Watchdog Timer (WDT) is a system function for monitoring correct program operation, mak-
ing it possible to recover from error situations, for instance run-away code. The WDT is a timer,
configured to a predefined timeout period and is constantly running when enabled. If the WDT is
not reset within the timeout period, it will issue a system reset. The WDT is reset by executing
the WDR (Watchdog Timer Reset) instruction from the application code.
The WDT also has a window mode that enables the user to define a time slot where WDT must
be reset within. If the WDT is reset too early or too late, a system reset will be issued.
The WDT will run in all power modes if enabled. It runs from a CPU independent clock source,
and will continue to operate to issue a system reset even if the main clocks fail.
The Configuration Change Protection mechanism ensures that the WDT settings cannot be
changed by accident. In addition the settings can be locked by a fuse.
In normal mode operation a single timeout period is set for the WDT. If the WDT is not reset from
the application code before the timeout occurs the WDT will issue a system reset. There are 11
possible WDT timeout (TO
any time during the period. After each reset, a new timeout period is started. The default timeout
period is controlled by fuses. Normal mode operation is illustrated in
Figure 11-1. Normal mode operation.
11 selectable timeout period, from 8 ms to 8s
Two operation modes
Runs from 1 kHz Ultra Low Power clock reference
Configuration lock
– Standard mode
– Window mode
TO
WDT
= 16
WDT Count
WDT
5
) periods selectable from 8 ms to 8s, and the WDT can be reset at
10
15
System Reset
20
Timely WDT
Reset
TO
25
WDT
30
Figure
35
WDT Timeout
11-1.
XMEGA A
t [ms]
117